1. Different computing devices in Arnoldβs home use different processor architectures. One processor architecture is the Harvard architecture.
a) Describe the Harvard architecture
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π Mark Scheme (a):
1 mark per bullet up to a maximum of 2 marks, e.g:
β’ Uses separate memory blocks for instructions and
data
β’ Has separate buses (data and address) for data and
instructions
β’ Has fixed memory sizes for data and Instructions
β’ Instruction memory may be ROM
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b) Arnold has a smart washing machine. Explain why the Harvard architecture is suitable for a device like this.
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π Mark Scheme (b):
1 mark per bullet up to a maximum of 2 marks, e.g:
β’ Fixed instruction size
β’ No need for memory to be shared between data and
instructions
β’ Removes need for secondary storage
β’ Instructions would never be changed
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2. A charity uses a desktop computer to record financial donations that it receives. The computer
contains a single core, 2.4GHz processor with 2MB cache.
(i) Describe what is meant by the term βVon Neumann architectureβ.
a) The processor uses the Von Neumann architecture.
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π Mark Scheme (a):
Both data and instructions share the same memory
Instructions and Data stored in same format
A single set of buses / same bus for instructions &
data (to connect CPU to Memory and I/O)
Has a (single) control unit
Has an ALU.
Has ways to input and output.
Has access to storage,
Works sequentially through instructions // follows
Fetch-execute cycle
(Special) registers within CPU
Based on stored program concept
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b) Give one way that the Harvard architecture differs from the Von Neumann architecture.
[1]
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π Mark Scheme (b):
Separate memory for data and instructions / Multiple
memory units
Different (sets of) buses one for instructions & one
for data/ instructions and data can be accessed
concurrently.
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3. The charity is concerned that the performance of the computer is not sufficient and wishes to
replace the processor.
Give two features of a replacement processor that would increase the typical performance of
the computer.
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π Mark Scheme:
Higher/faster clock speed
More cores//dual/quad/etc core
More cache memory.
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4. A program is run on a processor that allows pipelining.
Define the the term 'pipelining'
[3]
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π Mark Scheme:
One instruction can be fetched while another is
being decodedβ¦
β¦and another is executed
The output of one process/instruction is the input of
the next.
Concurrent processing of multiple instructions //
completing multiple FDE cycles at once
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5. A processor contains registers including the accumulator and the program counter. The contents of these registers are modified during the Fetch-Decode-Execute cycle.
a) Describe how the accumulator is used during the Fetch-Decode-Execute cycle.
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π Mark Scheme (a):
Holds all input/output
Holds results of calculations (from the ALU)
Checked for conditional branching (e.g. BRZ)
Stores data which has come from the MDR/RAM
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b) Describe how the program counter is used during the Fetch-Decode-Execute cycle.
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π Mark Scheme (b):
Holds the address/location of the next instruction (to
be executed/fetched)
Contents copied to the MAR at start of FDE
Incremented (by one) on every cycle
Can be changed by branch/jump instructions
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c) State the name of three other registers that are used during the Fetch-Decode-Execute cycle.
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π Mark Scheme (c):
Memory Address Register // MAR
Memory Data Register // MDR
Current Instruction Register // CIR
Index Register // IR